Method and system for screening logic circuits

ABSTRACT

A method of testing a circuit having one or more memory cells, such as a random access memory, register or latch, is disclosed herein. A selected pattern (e.g., all &#34;1&#34;s, all &#34;0&#34;s, or alternating &#34;1&#34;s and &#34;0&#34;s) is stored (block 10) in each memory cell of the circuit under test. The power to each of the cells is then lowered (block 12) to a selected voltage level which is below the static holding voltage. After a selected time period, the power to each of the cells is restored (block 14) and the logical state present in each cell is compared (block 16) with the initially stored logical state to determine if any of the cells have switched to another logical state. This procedure may be repeated (blocks 18-26) a number of times.

This invention was made with government support under Contract No.DNA001-C86-0090 awarded by the Defense Nuclear Agency. The Governmentmay have certain rights in this invention.

This a continuation of application Ser. No. 07/842,672 which was filedon Feb. 27, 1992, which was abandoned as part of a file wrappercontinuation of application Ser. No. 08/300,574, which was issued asU.S. Pat. No. 5,422,852 on Jun. 6, 1995.

FIELD OF THE INVENTION

This invention generally relates to integrated circuits, and moreparticularly to a method and apparatus for screening memory circuits forpreferred states to detect circuits having weak cells.

BACKGROUND OF THE INVENTION

To ensure the operability of a memory cell, including storage devicessuch as registers or latches, each individual device is usually testedafter fabrication. The devices are tested by storing a known patterninto the stored cells of the device and subsequently reading thecontents of the device. If the data input to the device is not identicalto the data output from the device, then the device is discarded ashaving one or more failed cells. To detect hard failures, where a memorycell is always one or always zero, the device is tested with differentpatterns, such that each cell is tested for its ability to successfullystore both logic states.

Where higher reliability is needed, more extensive testing may beperformed on the devices. For example, the devices may be tested atdifferent temperature ranges to ensure the operability of the deviceover a specified temperature range. Similarly, the device may be testedover a specified voltage range to determine failures. In some instances,the devices will be tested after a prescribed "burn-in" period,typically, 24 to 48 hours, wherein the device is operated during theburn-in period. If the device is likely to fail during operation, it hasbeen found that there is a high probability that the chip will failduring the burn-in period.

Nevertheless, the operational testing does not detect all errors whichmay occur due to processing variations and inaccuracies. A memory devicemay fail because some of its cells are "weak," i.e., they may be proneto upset, wherein the stored cell may flip from the stored logic stateto the complementary logic state. Upset may occur in a weak cell due toseveral external factors. Alpha particles emitted from the packagingmaterials may cause a weak memory cell to switch states. Similarly, ahigh energy ion may impinge the memory cell, leaving electron/hole pairswhich cause the cell to upset. This phenomena is known as single eventupset, or SEU. Further, a burst of gamma radiation may generate electronhole pairs which push the voltage toward the mid-rail, causing thememory cell to switch states. A memory device's immunity to gammaradiation is known as its transient dose hardness. It is also possiblethat as parameters change with time, for example with hot electrondegradation or with metal migration, a weak cell may become a failure.

Therefore, a need has arisen in the industry for a test which willdetect weak memory cells in a storage device.

SUMMARY OF THE INVENTION

Other objects and advantages will be obvious, and will in part appearhereinafter and will be accomplished by the present invention whichprovides a method and system for screening logic circuits.

A method of testing a circuit having one or more memory cells, such as arandom access memory, register or latch, is disclosed herein. A selectedpattern (e.g., all "1"s , all "0"s , or alternating "1"s and "0"s ) isstored in each memory cell of the circuit under test. The power to eachof the cells is then lowered to a selected voltage level which is belowthe minimum data holding level. The selected voltage level may have beenpreviously determined. After a selected time period (which may also havebeen previously determined), the power to each of the cells is restoredand the logical state present in each cell is compared with theinitially stored logical state to determine if any of the cells haveswitched to another logical state. This procedure may be repeated anumber of times.

The testing method may be used to test the reliability of a memorydevice or to categorize storage devices in different reliabilityclassifications. The classifications may be for varied threshold voltagelevels, nominal time periods or temperatures.

In a specific embodiment, a selected pattern (e.g., all "1"s ) is storedin each memory cell of the circuit under test. The power to each of thecells is then lowered below a selected threshold voltage level. After aselected time period, the power to each of the cells is restored. Thelogical state present in each cell is then compared with the selectedpattern to determine if any of the cells have switched to another state.The procedure is then repeated by storing the complement of theinitially selected pattern (e.g., all "0"s ) in each memory cell of thecircuit. The power to each of the cells is lowered below the selectedthreshold voltage level (which may or may not be the same as before) andafter a time period the power is restored. The logical state present ineach cell is once again compared with the stored complement logicalstate to determine if any of the cells have switched to another state.

This aspect of the present invention has the technical advantage thatcells having a preferred state can be detected. The more balanced thecell, the longer the stored state will be retained at the reduced powerlevel and/or the lower the threshold voltage may go. The more imbalancedthe cell, the sooner it will switch from the stored state to thepreferred state once power is interrupted. Cells having a preferredstate can be detected and classified as more prone to upset and ashaving a lower transient dose hardness.

Another aspect of the present invention will determine whether any cellsof the storage device have a preference toward either logical state.

In yet another aspect of the invention, the ability to classify storagedevices into various reliability categories for different applicationsis provided.

BRIEF DESCRIPTION OF THE DRAWINGS

The above features of the present invention will be more deaflyunderstood from consideration of the following descriptions inconnection with accompanying drawing in which:

FIG. 1 illustrates a flow chart describing the preferred embodimentscreening test of the present invention;

FIG. 2 illustrates a block diagram of an exemplary circuit forperforming the test of the present invention;

FIG. 3 illustrates a block diagram of a modified exemplary test system.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The making and use of the presently preferred embodiments are discussedbelow in detail. However, it should be appreciated that the presentinvention provides many applicable inventive concepts which can beembodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not delimit the scope of the invention.

The present invention is related to U.S. Pat. No. 5,023,874 by Houstonwhich was issued on Jun. 11, 1991 and is assigned to the assignee ofthis patent.

During the fabrication of an integrated circuit, processing variationsare certain to occur between different wafers, and between differentcircuits on a single wafer. For example, line widths, implant densities,and oxide thicknesses may vary from the optimum within a certain degreefrom circuit to circuit. To some extent, these variations are alwayspresent.

Processing variations may cause some cells to have a preference to alogical state, either a "1" or "0". As the voltage stored in the cellsapproaches a mid-rail between a logical "0" and a logical "1", thestorage cell will tend to latch onto the voltage in accordance with itspreference. In other words, a cell having a preference towards a logical"1" will respond to a voltage near the mid-rail as being set to a "1",while a cell having a preference towards logical "0" will tend torespond to a voltage near the mid-rail as being set to a "0". Thepreference may be either slight or strong depending on the degree ofprocess variations. In the extreme case, a cell may respond to all inputvoltages as either logical "1"s or logical "0"s .

Under normal circumstances, a storage cell with a preference willoperate normally if the preference is not too strong. However, lessperturbation, such as from alpha particles or high energy ions, isrequired to upset the cell from its unpreferred state to its preferredstate than would be required to upset a balanced cell.

Thus, by determining which devices have cells with preferred states,storage devices can be screened to determine those less likely toencounter upset.

A method for locating soft cells in a RAM is disclosed by Hardee et al.in U.S. Pat. No. 4,650,762 ('762). With this technique, a known logicpattern is written in the memory array and the wordlines for the arrayare sequentially subjected to a non standard test signal such as aslowly varying voltage. To implement the preferred embodiment, an accesspad is added for receipt of an externally generated test signal. Acentral circuit is also used to selectively couple the test signal tothe wordlines of the memory array.

The method disclosed in the '762 patent has several shortcomings. Sinceit is necessary to include a separate test pad and circuitry, valuablechip space is used and performance may be degraded. In addition, aspecial analog voltage signal (e.g., a sawtooth voltage waveform)applied to the wordlines. This signal must be generated especially forthis purpose.

The present invention, on the other hand, depends on varying the powersupply voltage (as opposed to the wordline voltage). As will bedescribed below, the power can be lowered or turned all the way off.This method provides an advantage because no additional test pads arerequired since the supply voltage is being effected. Other advantageswill also be apparent within the description below.

The preferred embodiment of the present invention is best understood byreferring to FIG. 1.

FIG. 1 illustrates a flow chart for a screening test to determine whichdevices have cells with preferred states. For purposes of illustration,FIG. 1 will be described in connection with a static random accessmemory (SRAM); however, it should be noted that the test illustrated inFIG. 1 should be able to determine weak cells in other devices such asregisters, latches, microprocessors having internal storage memories,pseudo-static DRAMs, FIFOs, and other devices.

In block 5, a selected voltage level and a selected time period aredetermined. The voltage level is below the static holding voltage (i.e.,below the minimum dataholding limit voltage). Details on the selectionof the voltage and time will be discussed hereinbelow.

In block 10, a pattern of logical values is stored into the SRAM. Forexample, a logical "1" (or logical "0") could be written into all thememory locations in the

In block 12, the power to the SRAM is lowered for a nominal time period.Here, the power is lowered below the selected voltage level which isbelow the static holding voltage. In other words, the power is loweredbelow a threshold at which the memory cell would normally lose storeddata if left there for a long enough period of time (which is longerthan the nominal time period referred to in block 12).

In block 14, the normal power is restored (i.e., returned to anoperating level at which data can be stored and maintained indefinitely)to the SRAM. Under normal circumstances, a fully discharged SRAM willhave random logical values in its cells at power-up. However, once datais written into the cells, the power may be lowered below the staticholding voltage (or even turned off) for a short time period without thedata being lost. If, however, the SRAM has one or more cells withpreferred logical states, those cells will likely switch to theirpreferred state when power is restored. Also, if the SRAM has cells withexcessive leakage, reduced capacitance, or weak drive currents, thesecells will more likely go to a random state, even if balanced. Thelonger the time period at low power (or power-off), the more likely thatthe cell with the preferred state will actually switch to that state orthat the balanced but otherwise weak cell will switch to a random state.

In block 16, the data is read from the SRAM and compared to the storedpattern in block 10. For example, if all "1"s were stored in block 10,the data read from the SRAM in block 16 should be all "1"s as well. Ifany "0"s are present, then it can be determined that the cell has apreference towards a logical "0".

In block 18, a complementary pattern is stored in the SRAM. Thus, if all"1"s were stored in block 10, then all "0"s would be stored in the SRAMin block 18. Once again, in block 20, the power is lowered for a nominaltime period. In block 22, power is restored and, in block 24, the bitpattern is read from the SRAM and, compared to the complementary patternstored in block 18. If one or more of the cells of the SRAM have stored"1"s, then the cells may be classified as having a preference towards alogical "1".

As illustrated by blocks 26 and 28, the test may be repeated with adifferent voltage levels and/or time periods. The test may also berepeated a number of times with the same time and voltage for greateraccuracy. By repeating the test, cells which may be weak in eitherdirection may be detected.

The test of the present invention is accomplished with the use ofcontrol circuits to adjust the value of the lowered power supply value,and a pulse generator or timing circuit to control the time that theSRAM is powered to the lower voltage. The value of the lowered voltageand the time at which it remains at the lowered value is dependent onthe technology and the memory cell design, but could be the same for agiven part type once the values have been established throughexperiment.

The circuitry that controls the lowering of the supply voltage must alsocontrol all signal voltages to that same level so that power is notsupplied through the signal inputs and input protection circuitry. Anenable circuit provides the modified supply and signal voltage high(V_(cc) ') and low (V_(ss) ') to the device under test. The V_(cc) ' isset to the nominal supply voltage level, while the V_(ss) ' is set tothe lowered voltage level. One specific example of a circuitimplementation will be described below with respect to FIG. 2.

To establish timing and voltage levels for screening of an SRAM or otherpart, an initial time and voltage level are selected, such as 0.1seconds and 0.5 volts. Then either the voltage or time is held constantwhile the other is varied to obtain a response of bit upsets as afunction of the two variables. From this response, the weak bitscreening test parameters can be established.

The nominal time period for power interruption may be determinedempirically by using a benchmark test cell. The test may be performed onthe benchmark test cell several times using increasingly longer timeperiods. At some point, the benchmark test cell will no longer be ableto retain this information and errors will be seen in blocks 16 and 24of FIG. 1. Using the longest time at which the benchmark test cell doesnot show errors as the nominal time period, devices may be classified inrelation to the benchmark. It should be noted that the nominal timeperiod may differ for different devices. For example, a 16K SRAM mayhave a different nominal time period than a 256K SRAM, even though theprobability of upset in both cells is substantially the same. Also, theinterrupt time may be set for a duration shorter than that found for thebenchmark cell.

Likewise, the threshold voltage below which the power is lowered (i.e.,a voltage below the minimum data holding voltage limit) may bedetermined empirically. This test may also be made using a benchmarkcell. The test may be performed on the benchmark test cell several timesusing increasingly low voltages with a given time period. In otherwords, the voltage level and time period may be determined in pairs. Forexample, if the power is turned completely off (e.g., the thresholdvoltage is zero volts), a selected nominal time will be determined. Thiswas the case discussed in the aforementioned U.S. Pat. No. 5,023,874('874). In other cases, the power is turned to a voltage greater thanzero and a different nominal time is determined.

The present invention has several advantages over the '874 patent. Themethod of turning the power fully off works well with memory cells whichhave a long dynamic hold time. However, if a memory cell has arelatively short dynamic hold time, turning the power fully off may notbe suitable. These cells are better suited for simply lowering thevoltage as described herein. This invention is important for cells notspecifically designed for high resistance to upset, and becomesespecially important as memory cells become smaller and therefore haveshorter dynamic hold times.

In SRAMs, information in the array will be maintained indefinitely aslong as the supply voltage is maintained above some minimum data-holdinglimit voltage. The information, however, may be lost if the supplyvoltage is lowered below the minimum data-holding voltage. Because ofcapacitance effects, the information will be retained if the supplyvoltage is briefly lowered below the minimum data-holding voltage andthen restored. The length of time that the voltage can be lowered belowthe minimum data-holding voltage without loss of information isdependant on how much the voltage is lowered. The lower the voltage, theshorter the time before the voltage must be restored for retention ofthe information. The duration of memory retention with the supplyvoltage below the minimum data-holding voltage is reduced by anyimbalance in the cell, particularly any imbalance in leakage currents ornode capacitances, as might be caused by defects.

One method of determining a threshold voltage is disclosed by Ohe inU.S. Pat. No. 4,553,225 ('225). In this patent, predetermined data iswritten into an IC memory at a normal-operation power-supply voltage,and the written data is read out and confirmed. Next, the power-supplyvoltage is lowered and is then returned to the normal-operationpower-supply voltage after a predetermined period of time has passed inorder to determine whether the stored data is in agreement with the dataas initially written. When the stored data is in agreement with the dataas initially written, the power-supply voltage is further lowered torepeat the above-mentioned procedure. The above-mentioned procedure isfurther repeated when the stored data is in agreement with the initiallywritten data and a minimum data-holding limit voltage which is capableof holding the written data is thereby determined.

In other words, the '225 patent teaches a method testing IC memorieswhich is capable of determining the minimum data-holding limit voltageof the memory cells, and further teaches the use of this method to findmemory elements that have an unstable cell margin.

The present invention, however, teaches the determination of theduration of data hold time for supply voltages below the minimumdata-holding limit voltage. The application of this method to thedetermination of memory elements that have imbalances is also described.One advantage of the present invention is that the dynamic test isparticularly sensitive to leakage currents and imbalances in leakagecurrent or node capacitances. Also, the flexibility of being able adjustthe combination of the dynamic holding voltage level and the duration ofthe lowered voltage allows optimization of the technique for a givencombination of integrated circuit memory technology and test equipment.For memory elements with relatively large capacitances, the drop involtage can be increased for faster test time. For memory elements withrelatively small capacitances, the voltage drop can be reduced toprovide a dynamic hold time in a range that is readily measured,according to the test equipment being used.

To summarize, in the present invention, a threshold voltage isdetermined. This threshold voltage may be determined using someempirical method or even a sequence of tests similar to those describedin the '225 patent. (A method similar to that of the '225 patent canonly be used if a nominal time period is first determined as discussedherein.) In addition, if the threshold voltage is known by other means,such as past experience for instance, this will count as the step ofdetermining.

In an alternative embodiment of the present invention, each cell istested over a range of interrupt times and/or threshold voltages untilfailure occurs, and the parts are categorized accordingly. In thisembodiment, one specific benchmark time period is not required.

Although FIG. 1 has been described using patterns of all "1"s and all"0"s , other patterns can be used if desired, such as alternating "0"sand "1"s. In some circumstances, the preference of one cell may beinfluenced by the value stored in adjacent cells; therefore, it may bedesirable to use a plurality of different patterns in testing thedevices. It is generally desirable that during the test each cell haveat least one logical "1" and one logical "0" written to it, such thatthe preference for either value may be determined.

Also, it should be noted that while FIG. 1 has been discussed inrelation to an SRAM, many different devices may also be tested using thepresent invention. Any device which has a plurality of states and whichwill dynamically retain state information for some period of reducedpower may be screened using the test of the present invention. Suchdevices would include registers, latches and similar devices used withinlarger integrated circuits such as microprocessors. It may also bepossible to use the present invention with pseudo-static DRAMs.

Additionally, the test of the present invention may be used inconjunction with other qualifying factors. For example, the test couldbe performed over different temperature and input voltage ranges, orother environmental ranges, to determine different classifications ofreliability. Further, the devices could be tested over a range ofnominal time periods, to determine the degree to which the devices areresistant to upset. Thus, the devices could be easily matched to thespecific applications in which they are used.

It should also be noted that this test can be used to qualify a wafer orlot for retention time as a combined test for capacitance, uniformityand leakage. Thus, the retention time for a "balanced" cell may bedetermined by following the procedure described above for determiningthe nominal time period for power interruption with a given voltagelevel.

An exemplary circuit implementation for performing the test of thepresent invention will now be described. Referring to FIG. 2, the testcircuit includes a power-off board 32 to be used on the MosAid MS2200tester 30. Although described herein with reference to the MS2200tester, as will be obvious to those skilled in the art, other testingsystems may also be used.

The circuitry described herein will allow the ability to perform thefollowing tests: 1) Search for weak bits--bits which do not retain theirdata as readily as other bits. 2) Memory retention--determination of thelength of time which a memory will retain a pattern which has beenwritten when the power has been disabled. 3) Power-ON/OFFglitch--examination of the power consumed upon enabling or disablingpower to the device.

The tester will be designed to be generic in the sense that one MS2200board will be used for all tests. This board will have signals broughtto a 40 pin ZIP socket 34 which will then be scrambled for theparticular device under test (DUT) 36.

The 40 pin ZIP socket 34 has pins with the following functions:

    ______________________________________                                        Pins Descriptions                                                             ______________________________________                                        1-22 Addresses A.sub.0 -A.sub.21, all of the available addresses.             1-8  Selectable between DQ.sub.0 -DQ.sub.7 for COMMON I/O or as                    DO.sub.0 -DO.sub.7 for SEPARATE I/O devices.                             1    DI for SEPARATE I/O devices.                                             2    CE.sub.1 and CE.sub.2 to allow for a maximum of two chip selects.        1    OE for output enable signal.                                             1    WE for write enable signal.                                              1    V.sub.ss.                                                                1    V.sub.bb.                                                                1    V.sub.cc.                                                                38   Total number of used pins.                                               ______________________________________                                    

Some of the signals will be gated with a control pulse while some willbe allowed to pass through a 3-state buffer. The following is a list ofthe signals and how they will be controlled.

    ______________________________________                                        Signals  How generated                                                        ______________________________________                                        GA.sub.0 -GA.sub.21                                                                    Addresses A.sub.0 -A.sub.21 gated through 74HC808 by                          external pulse.                                                      EDQ.sub.0 -EDQ.sub.7                                                                   COMMON I/O data lines with D.sub.0 -D.sub.7 enabled by                        WE pulse.                                                            GDI      SEPARATE I/O Data in gated through 74HC808                                    by ext. pulse.                                                       GCE.sub.1                                                                              CE gated through 74HC808 by external pulse.                          GCE.sub.2                                                                              C4 gated through 74HC808 by external pulse.                          GOE      OE gated through 74HC808 by external pulse.                          GWE      WE gated through 74HC808 by external pulse.                          GV.sub.cc                                                                              VCC produced from 74HC808 enabled by external                                 pulse (use two of the AND's in 74HC808 for                                    higher current.)                                                     ______________________________________                                    

It is noted that the 74HC808 is a HEX CMOS AND buffer and that five ofthese packages should typically suffice. There will be 29 signals gatedthrough the 74HC808 and 8 signals enabled through 3-state buffers.

The input from the enabling external pulse should typically be bufferedto provide enough drive for all 29 gates. This can be accomplished byusing a 74HC04 and buffered through one of the hex buffers in thispackage.

The 3-state signals can be easily generated using a 74HC244.

Typically, all signals will be driven to ground except the COMMON I/ODQ's which will have their inputs in 3-state (generally) and theiroutputs will pass back to the MosAid 2200.

The outputs will pass through the output load selection adapter whichwill use plug-ins to determine whether or not there is a load and ofwhat kind it will be. This will also allow for easy disconnect of theoutputs for active read power measurements.

In the preferred embodiment, the board will have the followingcomponents placed on it.

1. One 40 pin ZIP socket.

2. Five SN74HC808 I.C.'s which will be used to gate the signals.

3. One SN74HC244 I.C. which will be used to 3-state the data in lines.

4. One SN74HC04 I.C. to buffer the external gate pulse.

5. One 16 pin DIP type socket for Connect/Disconnect of theCOMMON/SEPARATE I/O lines.

6. One 16 pin DIP type socket for connecting the output data to theproper load.

7. One female BNC connector for the external pulse from generator.

8. One 50 ohm resistor for external pulse on BNC.

9. Two banana plugs for connecting external power supply for the gatesand buffers.

In one aspect, the key to the method of implementation discussed hereinis in the way in which the variable supply and signal levels to the DUTare obtained and controlled. In this example, the key is the use of thebuffer circuit with variable supply voltages. The V_(cc) ' supply to thebuffer is varied to control the DUT "on" V_(cc) level and the DUT V_(ih)signal levels. The V_(ss) ' supply is varied to control the DUT powerdown V_(cc) level and the DUT V_(il) signal levels. This circuit ensuresthat both the V_(cc) and the signal levels to the DUT are lowered to thesame preselected voltage for the screening test.

FIG. 3 illustrated a modification to the power-offboard which allows theuser to specify both V_(IH) and V_(IL) relative to ground. Referring toFIG. 3, the "enable" signal is the timing control for the power downtime, the DPS1 is the source V_(cc) supply in the memory tester, and the"sig" are the logic control signals from the memory tester. Signals A(DPS1) and B (enable) are ANDed together as well as signals A (sig) andB (enable) to control the timing of the screen test. Then the suppliesV_(ss) ' and V_(cc) ' control the voltage levels to the DUT as describedabove.

While this invention has been described with reference to illustrativeembodiments, this description is not intended to be construed in alimiting sense. Various modifications and combinations of theillustrative embodiments, as well as other embodiments of the invention,will be apparent to persons skilled in the art upon reference to thedescription. It is therefore intended that the appended claims encompassany such modifications or embodiments.

What is claimed is:
 1. A method of testing a circuit having one or morememory cells, comprising the steps of:determining a static holdingvoltage for said circuit under test; selecting a selected voltage levelwhich is below said static holding voltage; storing a logical stateaccording to a selected pattern in each of a plurality of memory cellsof said circuit under test; lowering the power to each of the pluralityof cells to said selected voltage level; restoring the power to each ofthe cells after a selected nominal time period; and comparing thelogical state present in each cell with said stored logical state afterpower has been restored to said cells to determine if any of the cellshave switched to another logical state.
 2. The method of claim 1 whereinsaid first selected voltage level is zero volts.
 3. The method of claim2 wherein said step of lowering the power comprises the step of turningthe power off.
 4. The method of claim 1 and further comprising the stepsof repeating said storing, lowering, restoring and comparing steps apredetermined number of times.
 5. The method of claim 1 and furthercomprising the steps of:storing selected logical states according to adifferent selected pattern in each memory cell of said circuitry undertest; lowering the power to each of the cells to a second selectedvoltage level; restoring the power to each of the cells after a selectedtime period; and comparing the logical state present in each cell withsaid different selected pattern after power has been turned restoredsaid cells to determine if any of the cells have switched to anotherlogical state.
 6. The method of claim 5 wherein the step of storingselected logical states according to a different selected patterncomprises storing the complement of the logical state previously storedin each memory cell under test.
 7. The method of claim 1 wherein saidselected pattern comprises all logical "1"s.
 8. The method of claim 1wherein said selected pattern comprises all logical "0"s.
 9. The methodof claim 1 wherein said selected pattern comprises a patten ofalternating logical "0"s and logical "1"s.
 10. The method of claim 1wherein said determining a static holding voltage comprises the step ofempirically determining said static holding voltage.
 11. The method ofclaim 10 wherein said determining a static holding voltage comprises thesteps of:writing predetermined data into said circuit under test at anormal-operation power-supply voltage; reading out and confirming saidpredetermined data; lowering the power to said circuit to a first level;returning to the normal-operation power-supply voltage after apredetermined period of time has passed in order to determine whetherthe presently stored data is in agreement with said predetermined data;if said presently stored data agrees with said predetermined data,lowering the power to said circuit to a level below said first level;repeating said returning and lowering steps until the presently storeddata is not in agreement with said predetermined data.
 12. The method ofclaim 1 wherein said static holding voltage is determined from pastexperience.
 13. A method of testing a storage device with one or morestorage cells comprising the steps of:determining a static holdingvoltage for said circuit under test; selecting a threshold voltage whichis lower than the static holding voltage; storing a logical stateaccording to a selected pattern in each memory cell of said circuitunder test; lowering the power to each of the cells below said selectedthreshold voltage level; restoring the power to each of the cells aftera nominal time period; comparing the logical state present in each cellwith said selected pattern after power has been restored to determine ifany of the cells have switched to another state; storing the complementof the logical state in each memory cell from that previously stored;lowering the power to each of the cells below said selected thresholdvoltage level; restoring the power to each of the cells after saidnominal time period; and comparing the logical state present in eachcell with said stored complement logical state after power has beenrestored to determine if any of the cells have switched to anotherstate.